The PCI-SIG has announced the completion of the PCIe 5.0 specification. In the history of PCI development, this may be the first time a new standard has been finished before the previous iteration had even launched in the consumer market.
“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”
The rapid launch of PCIe 5.0 is the result of PCIe 4.0’s massive delay. PCIe 1.0 became available in 2003, followed by PCIe 2.0 in 2007 and PCIe 3.0 in 2010. (These are the dates when the standards were completed, not when motherboard hardware became available). PCIe 4.0, in contrast, wasn’t actually completed until 2017. The long delay in 4.0’s launch means that 5.0 will likely be deployed relatively quickly. As always, PCIe 5.0 will remain backward compatible with previous PCIe versions.
It’s not clear how the market will react to the quick appearance of PCIe 5.0 versus 4.0. AMD, for example, clearly intends to adopt PCIe 4.0 for its third-generation Ryzen platform, but could theoretically be planning a relatively quick migration to PCIe 5.0. Intel could theoretically planning for a fast shift to PCIe 5.0 — or the two standards might co-exist in market, with PCIe 4.0 used for less-demanding applications, while maximum performance markets push for PCIe 5.0. We haven’t seen PCIe 5.0 used as a differentiator this way before in client PCs, however, and for good reason — up until now, it’s never particularly mattered. While multi-GPU configuration performance can be impacted by PCIe lane availability, single-GPU performance has never scaled well against PCIe lanes, and I don’t recall any instance of a new GPU scaling better on a new version of PCIe at launch as compared to the immediately previous standard.
The popularity of PCIe-based SSDs and the M.2 form factor, however, have changed things. While the gap between using an SSD and an HDD is still far larger than the improvements gained when moving from a standard SATA SSD to an M.2 drive, opening up the throttle on PCIe 5.0 will really give NAND and Optane room to stretch their collective legs. A PCIe 3.0 M.2 drive with an x4 connection provides up to 4GB/s of bandwidth in each direction. PCIe 4.0 doubles this to 8GB. PCIe 5.0 doubles it again, to 16GB.
Not only does this mean that even an x1 PCIe 5.0 link is now a heck of a lot more capable than it once was, it also means x4 drives are approaching theoretical transfer rates we used to associate with main memory not so long ago. This doesn’t actually mean NAND performs like RAM, of course. Neither Optane nor NAND are a replacement for DRAM in current client machines, and the latencies and sustained performance characteristics are entirely different. But the relatively quick jump from PCIe 3.0 to PCIe 5.0 means maximum storage performance could get substantially faster than it is already in a relatively short period of time.
The earliest we’d expect to see PCIe 5.0 adoption would be in 2020, and 2021 wouldn’t be crazy depending on how quickly Intel and AMD adopt the standard.
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- PCI Express 4.0 announced even though PCIe 3.0 has not matured yet