Intel May Deploy AVX-512 in Upcoming 10nm Cannon Lake CPUs

, Intel May Deploy AVX-512 in Upcoming 10nm Cannon Lake CPUs, #Bizwhiznetwork.com Innovation ΛI

When Intel launched Skylake-SP (aka the Core X-series) earlier this year, one of the major features of the product family, in addition to a revamped L2 cache structure, was its support for Intel’s latest SIMD instruction set, AVX-512. AVX-512 has previously been reserved for Intel’s HPC (High-Performance Computing) Knights Landing. But Intel launched it as a feature in some of its Xeon Scalable Processors and the Skylake-SP-derived Core i9 and Core i7 CPUs launched earlier this year.

The Core i9-7900X (10-core) and above, including the Core i9-7980XE, have two 512-bit AVX-512 ports, while the 8-core and six-core parts have a single port for FMA-512. This means the higher end CPUs can support much higher throughput (64 single-precision or 32 double-precision operations per cycle, compared with 32 SP/16 DP operations on the 7800X and 7820X).

Now, Intel’s own instruction set guidelines suggest AVX-512 will be coming to desktop CPUs with Cannon Lake. That’s an unexpected update, given that this instruction set has been almost entirely confined to the HPC world, where applications are specialized enough to justify the kind of painstaking optimization that squeezes maximum performance out of the underlying hardware. Easier software development is one reason we were once told some HPC labs were embracing Intel’s Xeon Phi in the first place, though that was several years ago.

, Intel May Deploy AVX-512 in Upcoming 10nm Cannon Lake CPUs, #Bizwhiznetwork.com Innovation ΛI

AVX-512 can deliver significant improvements and efficiency in appropriately optimized applications.

But here’s where things get a bit confusing, because unlike AVX or AVX2, AVX-512 comes in a lot of flavors, including:

AVX-512-F: Foundational support. Required for all AVX-512 products. Anything advertised as AVX-512-capable must support AVX-512-F.
AVX-512-CD: Conflict Detection. Allows a wider range of loops to be vectorized. Supported on Skylake-X (Skylake-SP and Skylake-X use the same architecture).
AVX-512-ER: Exponential and Reciprocal instructions designed to help implement transcendental operations. Supported in Knights Landing.
AVX-512-PF: New prefetch capabilities. Supported by Knights Landing.

All of the below operations were introduced with Skylake-X earlier this year:

AVX-512-BW: Byte and Word operations to cover 8-bit and 16-bit operations.
AVX-512-DQ: Doubleword and Quadword instructions. New 32-bit and 64-bit AVX-512 operations.
AVX-512-VL: Vector Length extensions. Allows AVX-512 to operate on XMM (128-bit) and YMM (256-bit) registers.

The following instructions will be introduced with Cannon Lake, in addition to AVX-512-F, AVX-512-CD, and all three Skylake-X capabilities):

AVX-512-IFMA: Integer Fused Multiply-Add with 52-bits of precision.
AVX-512-VBMI: Vector Byte Manipulation Instructions. Adds additional capabilities not in AVX-512-BW.

That’s a lot of AVX-512

It’s hard to say what kind of uptake we’ll see from this new SIMD instruction set. AVX and AVX2 may have boosted performance in specific applications. But they didn’t deliver the general speedups we saw from SSE2 when the Pentium 4 was relatively new. Some of that was due to the P4’s terrible performance in x87 code, which often lagged the P3, but that wasn’t the entire explanation. As new SIMD sets have rolled out, synthetic apps continue to show big gains and, as we’ve said, HPC and other well-optimized apps do as well–but the major push to optimize for later SIMD sets doesn’t seem to hit with the same intensity it used to.

AVX-512 has been designed to make it easier to move from AVX to AVX-512 than it was to shift from earlier versions of SSE to AVX or AVX2. Whether that’ll make a significant difference remains to be seen. Skylake-X chips throttle back significantly in AVX-512, which means we’ll need to see some significant improvements to deliver a net gain in various applications.

Cannon Lake is expected to debut in 2018.

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